The competition of chip products is increased day by day, wherein a printed circuit board of some chip products is compacted to two layers, one layer is an element layer and the other layer is a copper grounding layer, for reducing the cost. Referring to FIG. 1, FIG. 1 is a structural schematic view of a traditional chip structure, Components on a copper grounding layer is shown by diagonal lines. The chip structure 10 comprises a chip 11 (shown by double slashes) disposed on the element layer of the printed circuit board 14, a plurality of bypass capacitors 12 disposed near the power pins of the chip 11, and a power line 13 (shown by double slashes) disposed on the copper grounding layer; An end of the bypass capacitor 12 is connected with the power pins, and the other end of the bypass capacitor 12 is connected with the power line 13 of the copper grounding layer, so that the current is supplied stably and the impedance is reduced.
The power pins are disposed around the chip 11, e.g. a timing controller for generating high speed signals of Low Voltage Differential Signaling (LVDS), the bypass capacitors 12 near the power pins must to be designed as a low-impedance circuit, so the power line 13 of the chip structure 10 is provided like a ring as seen in FIG. 1. The power line 13 is reached to the copper grounding layer by through holes specifically, and the current of the power line 13 is fed in the bypass capacitors 12 on the copper grounding layer, respectively, so that the copper grounding layer is formed as a semi-circular package.
Therefore, grounding of the copper grounding layer is separated from the semi-circular package, so that the heat dissipation effect and the yield of the chip 11 are influenced.